2012-04-16 12:31:48 +00:00
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From 77da4ad0d8dfe7c5f46a06296a04a992a961c1a3 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 20 Mar 2012 13:05:11 +0100
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Subject: [PATCH 61/70] MIPS: adds dsl clocks
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---
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arch/mips/lantiq/xway/sysctrl.c | 15 +++++++++++++--
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1 files changed, 13 insertions(+), 2 deletions(-)
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -41,8 +41,9 @@
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#define PMU_PCI BIT(4)
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#define PMU_DMA BIT(5)
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#define PMU_USB0 BIT(5)
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+#define PMU_EPHY BIT(7) /* ase */
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#define PMU_SPI BIT(8)
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-#define PMU_EPHY BIT(7)
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+#define PMU_DFE BIT(9)
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#define PMU_EBU BIT(10)
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#define PMU_STP BIT(11)
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#define PMU_GPT BIT(12)
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2012-04-17 12:51:02 +00:00
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@@ -147,7 +148,7 @@ static int ltq_pci_ext_enable(struct clk
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2012-04-16 12:31:48 +00:00
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static void ltq_pci_ext_disable(struct clk *clk)
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{
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- /* enable external pci clock */
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+ /* disable external pci clock (internal) */
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ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
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CGU_IFCCR);
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ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
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@@ -246,6 +247,9 @@ void __init ltq_soc_init(void)
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clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
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clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
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clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
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+ clkdev_add_pmu("ltq_dsl", NULL, 0,
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+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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+ PMU_AHBS | PMU_DFE);
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} else if (ltq_is_vr9()) {
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clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
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ltq_vr9_fpi_hz());
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@@ -261,12 +265,19 @@ void __init ltq_soc_init(void)
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PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
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PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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PMU_PPE_QSB);
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+ clkdev_add_pmu("ltq_dsl", NULL, 0, PMU_DFE | PMU_AHBS);
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} else if (ltq_is_ar9()) {
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clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
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ltq_ar9_fpi_hz());
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clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
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+ clkdev_add_pmu("ltq_dsl", NULL, 0,
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+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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+ PMU_PPE_QSB | PMU_AHBS | PMU_DFE);
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} else {
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clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
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ltq_danube_io_region_clock());
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+ clkdev_add_pmu("ltq_dsl", NULL, 0,
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+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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+ PMU_PPE_QSB | PMU_AHBS | PMU_DFE);
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}
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}
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