mirror of https://github.com/hak5/openwrt-owl.git
81 lines
2.4 KiB
Diff
81 lines
2.4 KiB
Diff
|
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||
|
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||
|
@@ -476,15 +476,21 @@
|
||
|
|
||
|
clocks = <&gcc PCIE_A_CLK>,
|
||
|
<&gcc PCIE_H_CLK>,
|
||
|
- <&gcc PCIE_PHY_CLK>;
|
||
|
- clock-names = "core", "iface", "phy";
|
||
|
+ <&gcc PCIE_PHY_CLK>,
|
||
|
+ <&gcc PCIE_AUX_CLK>,
|
||
|
+ <&gcc PCIE_ALT_REF_CLK>;
|
||
|
+ clock-names = "core", "iface", "phy", "aux", "ref";
|
||
|
+
|
||
|
+ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
|
||
|
+ assigned-clock-rates = <100000000>;
|
||
|
|
||
|
resets = <&gcc PCIE_ACLK_RESET>,
|
||
|
<&gcc PCIE_HCLK_RESET>,
|
||
|
<&gcc PCIE_POR_RESET>,
|
||
|
<&gcc PCIE_PCI_RESET>,
|
||
|
- <&gcc PCIE_PHY_RESET>;
|
||
|
- reset-names = "axi", "ahb", "por", "pci", "phy";
|
||
|
+ <&gcc PCIE_PHY_RESET>,
|
||
|
+ <&gcc PCIE_EXT_RESET>;
|
||
|
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||
|
|
||
|
pinctrl-0 = <&pcie0_pins>;
|
||
|
pinctrl-names = "default";
|
||
|
@@ -522,15 +528,21 @@
|
||
|
|
||
|
clocks = <&gcc PCIE_1_A_CLK>,
|
||
|
<&gcc PCIE_1_H_CLK>,
|
||
|
- <&gcc PCIE_1_PHY_CLK>;
|
||
|
- clock-names = "core", "iface", "phy";
|
||
|
+ <&gcc PCIE_1_PHY_CLK>,
|
||
|
+ <&gcc PCIE_1_AUX_CLK>,
|
||
|
+ <&gcc PCIE_1_ALT_REF_CLK>;
|
||
|
+ clock-names = "core", "iface", "phy", "aux", "ref";
|
||
|
+
|
||
|
+ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
|
||
|
+ assigned-clock-rates = <100000000>;
|
||
|
|
||
|
resets = <&gcc PCIE_1_ACLK_RESET>,
|
||
|
<&gcc PCIE_1_HCLK_RESET>,
|
||
|
<&gcc PCIE_1_POR_RESET>,
|
||
|
<&gcc PCIE_1_PCI_RESET>,
|
||
|
- <&gcc PCIE_1_PHY_RESET>;
|
||
|
- reset-names = "axi", "ahb", "por", "pci", "phy";
|
||
|
+ <&gcc PCIE_1_PHY_RESET>,
|
||
|
+ <&gcc PCIE_1_EXT_RESET>;
|
||
|
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||
|
|
||
|
pinctrl-0 = <&pcie1_pins>;
|
||
|
pinctrl-names = "default";
|
||
|
@@ -568,15 +580,21 @@
|
||
|
|
||
|
clocks = <&gcc PCIE_2_A_CLK>,
|
||
|
<&gcc PCIE_2_H_CLK>,
|
||
|
- <&gcc PCIE_2_PHY_CLK>;
|
||
|
- clock-names = "core", "iface", "phy";
|
||
|
+ <&gcc PCIE_2_PHY_CLK>,
|
||
|
+ <&gcc PCIE_2_AUX_CLK>,
|
||
|
+ <&gcc PCIE_2_ALT_REF_CLK>;
|
||
|
+ clock-names = "core", "iface", "phy", "aux", "ref";
|
||
|
+
|
||
|
+ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
|
||
|
+ assigned-clock-rates = <100000000>;
|
||
|
|
||
|
resets = <&gcc PCIE_2_ACLK_RESET>,
|
||
|
<&gcc PCIE_2_HCLK_RESET>,
|
||
|
<&gcc PCIE_2_POR_RESET>,
|
||
|
<&gcc PCIE_2_PCI_RESET>,
|
||
|
- <&gcc PCIE_2_PHY_RESET>;
|
||
|
- reset-names = "axi", "ahb", "por", "pci", "phy";
|
||
|
+ <&gcc PCIE_2_PHY_RESET>,
|
||
|
+ <&gcc PCIE_2_EXT_RESET>;
|
||
|
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||
|
|
||
|
pinctrl-0 = <&pcie2_pins>;
|
||
|
pinctrl-names = "default";
|