mirror of https://github.com/hak5/openwrt-owl.git
188 lines
9.5 KiB
Diff
188 lines
9.5 KiB
Diff
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From 45ff9697ed1668e82ca3902b32309e157464e745 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Thu, 6 Feb 2014 09:55:57 +0100
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Subject: [PATCH] clk: sunxi: Add new clock compatibles
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The Allwinner A10 compatibles were following a slightly different compatible
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patterns than the rest of the SoCs for historical reasons. Add compatibles
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matching the other pattern to the clock driver for consistency, and keep the
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older one for backward compatibility.
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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---
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Documentation/devicetree/bindings/clock/sunxi.txt | 36 +++++++++++------------
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drivers/clk/sunxi/clk-sunxi.c | 30 +++++++++----------
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2 files changed, 33 insertions(+), 33 deletions(-)
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diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
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index 256a908..a5160d8 100644
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--- a/Documentation/devicetree/bindings/clock/sunxi.txt
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+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
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@@ -6,37 +6,37 @@ This binding uses the common clock binding[1].
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Required properties:
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- compatible : shall be one of the following:
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- "allwinner,sun4i-osc-clk" - for a gatable oscillator
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- "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
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+ "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
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+ "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
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"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
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- "allwinner,sun4i-pll5-clk" - for the PLL5 clock
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- "allwinner,sun4i-pll6-clk" - for the PLL6 clock
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+ "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
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+ "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
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"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
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- "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
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- "allwinner,sun4i-axi-clk" - for the AXI clock
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- "allwinner,sun4i-axi-gates-clk" - for the AXI gates
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- "allwinner,sun4i-ahb-clk" - for the AHB clock
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- "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
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+ "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
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+ "allwinner,sun4i-a10-axi-clk" - for the AXI clock
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+ "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
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+ "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
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+ "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
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"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
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"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
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"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
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"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
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"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
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- "allwinner,sun4i-apb0-clk" - for the APB0 clock
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- "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
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+ "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
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+ "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
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"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
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"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
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"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
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- "allwinner,sun4i-apb1-clk" - for the APB1 clock
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- "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
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- "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
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+ "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
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+ "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
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+ "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
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"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
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"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
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"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
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"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
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"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
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"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
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- "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
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+ "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
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"allwinner,sun7i-a20-out-clk" - for the external output clocks
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"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
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"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
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@@ -69,7 +69,7 @@ For example:
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osc24M: clk@01c20050 {
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#clock-cells = <0>;
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- compatible = "allwinner,sun4i-osc-clk";
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+ compatible = "allwinner,sun4i-a10-osc-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc24M_fixed>;
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clock-output-names = "osc24M";
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@@ -77,7 +77,7 @@ osc24M: clk@01c20050 {
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pll1: clk@01c20000 {
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#clock-cells = <0>;
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- compatible = "allwinner,sun4i-pll1-clk";
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+ compatible = "allwinner,sun4i-a10-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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@@ -93,7 +93,7 @@ pll5: clk@01c20020 {
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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- compatible = "allwinner,sun4i-cpu-clk";
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+ compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>;
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clock-output-names = "cpu";
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index 335c987..23baad9 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -80,7 +80,7 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)
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err_free_fixed:
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kfree(fixed);
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}
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-CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
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+CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-a10-osc-clk", sun4i_osc_clk_setup);
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@@ -1207,52 +1207,52 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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/* Matches for factors clocks */
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static const struct of_device_id clk_factors_match[] __initconst = {
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- {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
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+ {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
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{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
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{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
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- {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
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- {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
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+ {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
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+ {.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
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{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
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{}
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};
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/* Matches for divider clocks */
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static const struct of_device_id clk_div_match[] __initconst = {
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- {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,},
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- {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,},
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- {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,},
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+ {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
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+ {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
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+ {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
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{.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
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{}
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};
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/* Matches for divided outputs */
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static const struct of_device_id clk_divs_match[] __initconst = {
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- {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
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- {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
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+ {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
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+ {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
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{}
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};
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/* Matches for mux clocks */
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static const struct of_device_id clk_mux_match[] __initconst = {
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- {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
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- {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
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+ {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
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+ {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
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{.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
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{}
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};
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/* Matches for gate clocks */
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static const struct of_device_id clk_gates_match[] __initconst = {
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- {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
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- {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
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+ {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
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+ {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
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{.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
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{.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
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{.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
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{.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
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- {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
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+ {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
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{.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
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{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
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{.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
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- {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
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+ {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
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{.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
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{.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
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{.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
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--
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2.0.3
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