mirror of https://github.com/hak5/openwrt-owl.git
789 lines
20 KiB
Diff
789 lines
20 KiB
Diff
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From 00009eabeb2074bef5c89e576a7a6d827c12c3d9 Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Wed, 29 Jan 2014 16:17:30 -0600
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Subject: [PATCH 004/182] clocksource: qcom: Move clocksource code out of
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mach-msm
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We intend to share the clocksource code for MSM platforms between legacy
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and multiplatform supported qcom SoCs.
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Acked-by: Olof Johansson <olof@lixom.net>
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/mach-msm/Kconfig | 13 +-
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arch/arm/mach-msm/Makefile | 1 -
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arch/arm/mach-msm/timer.c | 333 --------------------------------------
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drivers/clocksource/Kconfig | 3 +
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drivers/clocksource/Makefile | 1 +
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drivers/clocksource/qcom-timer.c | 329 +++++++++++++++++++++++++++++++++++++
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6 files changed, 338 insertions(+), 342 deletions(-)
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delete mode 100644 arch/arm/mach-msm/timer.c
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create mode 100644 drivers/clocksource/qcom-timer.c
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diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
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index 9625cf3..3c4eca7 100644
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--- a/arch/arm/mach-msm/Kconfig
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+++ b/arch/arm/mach-msm/Kconfig
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@@ -21,7 +21,7 @@ config ARCH_MSM8X60
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select CPU_V7
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select HAVE_SMP
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select MSM_SCM if SMP
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- select MSM_TIMER
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+ select CLKSRC_QCOM
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config ARCH_MSM8960
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bool "Enable support for MSM8960"
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@@ -29,7 +29,7 @@ config ARCH_MSM8960
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select CPU_V7
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select HAVE_SMP
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select MSM_SCM if SMP
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- select MSM_TIMER
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+ select CLKSRC_QCOM
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config ARCH_MSM8974
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bool "Enable support for MSM8974"
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@@ -54,7 +54,7 @@ config ARCH_MSM7X00A
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select MACH_TROUT if !MACH_HALIBUT
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select MSM_PROC_COMM
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select MSM_SMD
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- select MSM_TIMER
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+ select CLKSRC_QCOM
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select MSM_SMD_PKG3
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config ARCH_MSM7X30
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@@ -66,7 +66,7 @@ config ARCH_MSM7X30
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select MSM_GPIOMUX
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select MSM_PROC_COMM
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select MSM_SMD
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- select MSM_TIMER
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+ select CLKSRC_QCOM
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select MSM_VIC
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config ARCH_QSD8X50
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@@ -78,7 +78,7 @@ config ARCH_QSD8X50
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select MSM_GPIOMUX
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select MSM_PROC_COMM
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select MSM_SMD
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- select MSM_TIMER
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+ select CLKSRC_QCOM
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select MSM_VIC
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endchoice
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@@ -153,7 +153,4 @@ config MSM_GPIOMUX
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config MSM_SCM
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bool
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-config MSM_TIMER
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- bool
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-
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endif
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diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
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index 8327f60..04b1bee 100644
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--- a/arch/arm/mach-msm/Makefile
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+++ b/arch/arm/mach-msm/Makefile
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@@ -1,4 +1,3 @@
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-obj-$(CONFIG_MSM_TIMER) += timer.o
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obj-$(CONFIG_MSM_PROC_COMM) += clock.o
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obj-$(CONFIG_MSM_VIC) += irq-vic.o
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diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
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deleted file mode 100644
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index fd16449..0000000
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--- a/arch/arm/mach-msm/timer.c
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+++ /dev/null
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@@ -1,333 +0,0 @@
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-/*
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- *
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- * Copyright (C) 2007 Google, Inc.
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- * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
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- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- *
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- */
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-
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-#include <linux/clocksource.h>
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-#include <linux/clockchips.h>
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-#include <linux/cpu.h>
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-#include <linux/init.h>
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-#include <linux/interrupt.h>
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-#include <linux/irq.h>
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-#include <linux/io.h>
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-#include <linux/of.h>
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-#include <linux/of_address.h>
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-#include <linux/of_irq.h>
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-#include <linux/sched_clock.h>
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-
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-#include <asm/mach/time.h>
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-
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-#include "common.h"
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-
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-#define TIMER_MATCH_VAL 0x0000
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-#define TIMER_COUNT_VAL 0x0004
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-#define TIMER_ENABLE 0x0008
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-#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
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-#define TIMER_ENABLE_EN BIT(0)
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-#define TIMER_CLEAR 0x000C
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-#define DGT_CLK_CTL 0x10
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-#define DGT_CLK_CTL_DIV_4 0x3
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-#define TIMER_STS_GPT0_CLR_PEND BIT(10)
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-
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-#define GPT_HZ 32768
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-
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-#define MSM_DGT_SHIFT 5
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-
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-static void __iomem *event_base;
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-static void __iomem *sts_base;
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-
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-static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
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-{
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- struct clock_event_device *evt = dev_id;
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- /* Stop the timer tick */
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- if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
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- u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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- ctrl &= ~TIMER_ENABLE_EN;
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- writel_relaxed(ctrl, event_base + TIMER_ENABLE);
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- }
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- evt->event_handler(evt);
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- return IRQ_HANDLED;
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-}
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-
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-static int msm_timer_set_next_event(unsigned long cycles,
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- struct clock_event_device *evt)
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-{
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- u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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-
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- ctrl &= ~TIMER_ENABLE_EN;
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- writel_relaxed(ctrl, event_base + TIMER_ENABLE);
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-
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- writel_relaxed(ctrl, event_base + TIMER_CLEAR);
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- writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
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-
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- if (sts_base)
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- while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
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- cpu_relax();
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-
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- writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
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- return 0;
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-}
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-
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-static void msm_timer_set_mode(enum clock_event_mode mode,
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- struct clock_event_device *evt)
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-{
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- u32 ctrl;
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-
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- ctrl = readl_relaxed(event_base + TIMER_ENABLE);
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- ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
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-
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- switch (mode) {
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- case CLOCK_EVT_MODE_RESUME:
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- case CLOCK_EVT_MODE_PERIODIC:
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- break;
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- case CLOCK_EVT_MODE_ONESHOT:
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- /* Timer is enabled in set_next_event */
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- break;
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- case CLOCK_EVT_MODE_UNUSED:
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- case CLOCK_EVT_MODE_SHUTDOWN:
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- break;
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- }
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- writel_relaxed(ctrl, event_base + TIMER_ENABLE);
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-}
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-
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-static struct clock_event_device __percpu *msm_evt;
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-
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-static void __iomem *source_base;
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-
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-static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
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-{
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- return readl_relaxed(source_base + TIMER_COUNT_VAL);
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-}
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-
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-static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
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-{
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- /*
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- * Shift timer count down by a constant due to unreliable lower bits
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- * on some targets.
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- */
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- return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
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-}
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-
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-static struct clocksource msm_clocksource = {
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- .name = "dg_timer",
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- .rating = 300,
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- .read = msm_read_timer_count,
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- .mask = CLOCKSOURCE_MASK(32),
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- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
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-};
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-
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-static int msm_timer_irq;
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-static int msm_timer_has_ppi;
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-
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-static int msm_local_timer_setup(struct clock_event_device *evt)
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-{
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- int cpu = smp_processor_id();
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- int err;
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-
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- evt->irq = msm_timer_irq;
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- evt->name = "msm_timer";
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- evt->features = CLOCK_EVT_FEAT_ONESHOT;
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- evt->rating = 200;
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- evt->set_mode = msm_timer_set_mode;
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- evt->set_next_event = msm_timer_set_next_event;
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- evt->cpumask = cpumask_of(cpu);
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-
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- clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
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-
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- if (msm_timer_has_ppi) {
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- enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
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- } else {
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- err = request_irq(evt->irq, msm_timer_interrupt,
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- IRQF_TIMER | IRQF_NOBALANCING |
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- IRQF_TRIGGER_RISING, "gp_timer", evt);
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- if (err)
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- pr_err("request_irq failed\n");
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- }
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-
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- return 0;
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-}
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-
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-static void msm_local_timer_stop(struct clock_event_device *evt)
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-{
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- evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
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- disable_percpu_irq(evt->irq);
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-}
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-
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-static int msm_timer_cpu_notify(struct notifier_block *self,
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- unsigned long action, void *hcpu)
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-{
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- /*
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- * Grab cpu pointer in each case to avoid spurious
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- * preemptible warnings
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- */
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- switch (action & ~CPU_TASKS_FROZEN) {
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- case CPU_STARTING:
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- msm_local_timer_setup(this_cpu_ptr(msm_evt));
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- break;
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- case CPU_DYING:
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- msm_local_timer_stop(this_cpu_ptr(msm_evt));
|
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- break;
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- }
|
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|
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-
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|
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- return NOTIFY_OK;
|
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|
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-}
|
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|
|
-
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|
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-static struct notifier_block msm_timer_cpu_nb = {
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|
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- .notifier_call = msm_timer_cpu_notify,
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-};
|
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|
|
-
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|
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-static u64 notrace msm_sched_clock_read(void)
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-{
|
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|
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- return msm_clocksource.read(&msm_clocksource);
|
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|
|
-}
|
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|
|
-
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||
|
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-static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
|
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|
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- bool percpu)
|
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-{
|
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|
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- struct clocksource *cs = &msm_clocksource;
|
||
|
|
- int res = 0;
|
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|
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-
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||
|
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- msm_timer_irq = irq;
|
||
|
|
- msm_timer_has_ppi = percpu;
|
||
|
|
-
|
||
|
|
- msm_evt = alloc_percpu(struct clock_event_device);
|
||
|
|
- if (!msm_evt) {
|
||
|
|
- pr_err("memory allocation failed for clockevents\n");
|
||
|
|
- goto err;
|
||
|
|
- }
|
||
|
|
-
|
||
|
|
- if (percpu)
|
||
|
|
- res = request_percpu_irq(irq, msm_timer_interrupt,
|
||
|
|
- "gp_timer", msm_evt);
|
||
|
|
-
|
||
|
|
- if (res) {
|
||
|
|
- pr_err("request_percpu_irq failed\n");
|
||
|
|
- } else {
|
||
|
|
- res = register_cpu_notifier(&msm_timer_cpu_nb);
|
||
|
|
- if (res) {
|
||
|
|
- free_percpu_irq(irq, msm_evt);
|
||
|
|
- goto err;
|
||
|
|
- }
|
||
|
|
-
|
||
|
|
- /* Immediately configure the timer on the boot CPU */
|
||
|
|
- msm_local_timer_setup(__this_cpu_ptr(msm_evt));
|
||
|
|
- }
|
||
|
|
-
|
||
|
|
-err:
|
||
|
|
- writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
|
||
|
|
- res = clocksource_register_hz(cs, dgt_hz);
|
||
|
|
- if (res)
|
||
|
|
- pr_err("clocksource_register failed\n");
|
||
|
|
- sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
|
||
|
|
-}
|
||
|
|
-
|
||
|
|
-#ifdef CONFIG_OF
|
||
|
|
-static void __init msm_dt_timer_init(struct device_node *np)
|
||
|
|
-{
|
||
|
|
- u32 freq;
|
||
|
|
- int irq;
|
||
|
|
- struct resource res;
|
||
|
|
- u32 percpu_offset;
|
||
|
|
- void __iomem *base;
|
||
|
|
- void __iomem *cpu0_base;
|
||
|
|
-
|
||
|
|
- base = of_iomap(np, 0);
|
||
|
|
- if (!base) {
|
||
|
|
- pr_err("Failed to map event base\n");
|
||
|
|
- return;
|
||
|
|
- }
|
||
|
|
-
|
||
|
|
- /* We use GPT0 for the clockevent */
|
||
|
|
- irq = irq_of_parse_and_map(np, 1);
|
||
|
|
- if (irq <= 0) {
|
||
|
|
- pr_err("Can't get irq\n");
|
||
|
|
- return;
|
||
|
|
- }
|
||
|
|
-
|
||
|
|
- /* We use CPU0's DGT for the clocksource */
|
||
|
|
- if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
|
||
|
|
- percpu_offset = 0;
|
||
|
|
-
|
||
|
|
- if (of_address_to_resource(np, 0, &res)) {
|
||
|
|
- pr_err("Failed to parse DGT resource\n");
|
||
|
|
- return;
|
||
|
|
- }
|
||
|
|
-
|
||
|
|
- cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
|
||
|
|
- if (!cpu0_base) {
|
||
|
|
- pr_err("Failed to map source base\n");
|
||
|
|
- return;
|
||
|
|
- }
|
||
|
|
-
|
||
|
|
- if (of_property_read_u32(np, "clock-frequency", &freq)) {
|
||
|
|
- pr_err("Unknown frequency\n");
|
||
|
|
- return;
|
||
|
|
- }
|
||
|
|
-
|
||
|
|
- event_base = base + 0x4;
|
||
|
|
- sts_base = base + 0x88;
|
||
|
|
- source_base = cpu0_base + 0x24;
|
||
|
|
- freq /= 4;
|
||
|
|
- writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
|
||
|
|
-
|
||
|
|
- msm_timer_init(freq, 32, irq, !!percpu_offset);
|
||
|
|
-}
|
||
|
|
-CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
|
||
|
|
-CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
|
||
|
|
-#endif
|
||
|
|
-
|
||
|
|
-static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
|
||
|
|
- u32 sts)
|
||
|
|
-{
|
||
|
|
- void __iomem *base;
|
||
|
|
-
|
||
|
|
- base = ioremap(addr, SZ_256);
|
||
|
|
- if (!base) {
|
||
|
|
- pr_err("Failed to map timer base\n");
|
||
|
|
- return -ENOMEM;
|
||
|
|
- }
|
||
|
|
- event_base = base + event;
|
||
|
|
- source_base = base + source;
|
||
|
|
- if (sts)
|
||
|
|
- sts_base = base + sts;
|
||
|
|
-
|
||
|
|
- return 0;
|
||
|
|
-}
|
||
|
|
-
|
||
|
|
-void __init msm7x01_timer_init(void)
|
||
|
|
-{
|
||
|
|
- struct clocksource *cs = &msm_clocksource;
|
||
|
|
-
|
||
|
|
- if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
|
||
|
|
- return;
|
||
|
|
- cs->read = msm_read_timer_count_shift;
|
||
|
|
- cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
|
||
|
|
- /* 600 KHz */
|
||
|
|
- msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
|
||
|
|
- false);
|
||
|
|
-}
|
||
|
|
-
|
||
|
|
-void __init msm7x30_timer_init(void)
|
||
|
|
-{
|
||
|
|
- if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
|
||
|
|
- return;
|
||
|
|
- msm_timer_init(24576000 / 4, 32, 1, false);
|
||
|
|
-}
|
||
|
|
-
|
||
|
|
-void __init qsd8x50_timer_init(void)
|
||
|
|
-{
|
||
|
|
- if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
|
||
|
|
- return;
|
||
|
|
- msm_timer_init(19200000 / 4, 32, 7, false);
|
||
|
|
-}
|
||
|
|
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
|
||
|
|
index cd6950f..6510ec4 100644
|
||
|
|
--- a/drivers/clocksource/Kconfig
|
||
|
|
+++ b/drivers/clocksource/Kconfig
|
||
|
|
@@ -140,3 +140,6 @@ config VF_PIT_TIMER
|
||
|
|
bool
|
||
|
|
help
|
||
|
|
Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
|
||
|
|
+
|
||
|
|
+config CLKSRC_QCOM
|
||
|
|
+ bool
|
||
|
|
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
|
||
|
|
index c7ca50a..2e0c0cc 100644
|
||
|
|
--- a/drivers/clocksource/Makefile
|
||
|
|
+++ b/drivers/clocksource/Makefile
|
||
|
|
@@ -32,6 +32,7 @@ obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o
|
||
|
|
obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
|
||
|
|
obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
|
||
|
|
obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
|
||
|
|
+obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
|
||
|
|
|
||
|
|
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
|
||
|
|
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
|
||
|
|
diff --git a/drivers/clocksource/qcom-timer.c b/drivers/clocksource/qcom-timer.c
|
||
|
|
new file mode 100644
|
||
|
|
index 0000000..dca829e
|
||
|
|
--- /dev/null
|
||
|
|
+++ b/drivers/clocksource/qcom-timer.c
|
||
|
|
@@ -0,0 +1,329 @@
|
||
|
|
+/*
|
||
|
|
+ *
|
||
|
|
+ * Copyright (C) 2007 Google, Inc.
|
||
|
|
+ * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
|
||
|
|
+ *
|
||
|
|
+ * This software is licensed under the terms of the GNU General Public
|
||
|
|
+ * License version 2, as published by the Free Software Foundation, and
|
||
|
|
+ * may be copied, distributed, and modified under those terms.
|
||
|
|
+ *
|
||
|
|
+ * This program is distributed in the hope that it will be useful,
|
||
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||
|
|
+ * GNU General Public License for more details.
|
||
|
|
+ *
|
||
|
|
+ */
|
||
|
|
+
|
||
|
|
+#include <linux/clocksource.h>
|
||
|
|
+#include <linux/clockchips.h>
|
||
|
|
+#include <linux/cpu.h>
|
||
|
|
+#include <linux/init.h>
|
||
|
|
+#include <linux/interrupt.h>
|
||
|
|
+#include <linux/irq.h>
|
||
|
|
+#include <linux/io.h>
|
||
|
|
+#include <linux/of.h>
|
||
|
|
+#include <linux/of_address.h>
|
||
|
|
+#include <linux/of_irq.h>
|
||
|
|
+#include <linux/sched_clock.h>
|
||
|
|
+
|
||
|
|
+#define TIMER_MATCH_VAL 0x0000
|
||
|
|
+#define TIMER_COUNT_VAL 0x0004
|
||
|
|
+#define TIMER_ENABLE 0x0008
|
||
|
|
+#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
|
||
|
|
+#define TIMER_ENABLE_EN BIT(0)
|
||
|
|
+#define TIMER_CLEAR 0x000C
|
||
|
|
+#define DGT_CLK_CTL 0x10
|
||
|
|
+#define DGT_CLK_CTL_DIV_4 0x3
|
||
|
|
+#define TIMER_STS_GPT0_CLR_PEND BIT(10)
|
||
|
|
+
|
||
|
|
+#define GPT_HZ 32768
|
||
|
|
+
|
||
|
|
+#define MSM_DGT_SHIFT 5
|
||
|
|
+
|
||
|
|
+static void __iomem *event_base;
|
||
|
|
+static void __iomem *sts_base;
|
||
|
|
+
|
||
|
|
+static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
|
||
|
|
+{
|
||
|
|
+ struct clock_event_device *evt = dev_id;
|
||
|
|
+ /* Stop the timer tick */
|
||
|
|
+ if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
|
||
|
|
+ u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
|
||
|
|
+ ctrl &= ~TIMER_ENABLE_EN;
|
||
|
|
+ writel_relaxed(ctrl, event_base + TIMER_ENABLE);
|
||
|
|
+ }
|
||
|
|
+ evt->event_handler(evt);
|
||
|
|
+ return IRQ_HANDLED;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static int msm_timer_set_next_event(unsigned long cycles,
|
||
|
|
+ struct clock_event_device *evt)
|
||
|
|
+{
|
||
|
|
+ u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
|
||
|
|
+
|
||
|
|
+ ctrl &= ~TIMER_ENABLE_EN;
|
||
|
|
+ writel_relaxed(ctrl, event_base + TIMER_ENABLE);
|
||
|
|
+
|
||
|
|
+ writel_relaxed(ctrl, event_base + TIMER_CLEAR);
|
||
|
|
+ writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
|
||
|
|
+
|
||
|
|
+ if (sts_base)
|
||
|
|
+ while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
|
||
|
|
+ cpu_relax();
|
||
|
|
+
|
||
|
|
+ writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static void msm_timer_set_mode(enum clock_event_mode mode,
|
||
|
|
+ struct clock_event_device *evt)
|
||
|
|
+{
|
||
|
|
+ u32 ctrl;
|
||
|
|
+
|
||
|
|
+ ctrl = readl_relaxed(event_base + TIMER_ENABLE);
|
||
|
|
+ ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
|
||
|
|
+
|
||
|
|
+ switch (mode) {
|
||
|
|
+ case CLOCK_EVT_MODE_RESUME:
|
||
|
|
+ case CLOCK_EVT_MODE_PERIODIC:
|
||
|
|
+ break;
|
||
|
|
+ case CLOCK_EVT_MODE_ONESHOT:
|
||
|
|
+ /* Timer is enabled in set_next_event */
|
||
|
|
+ break;
|
||
|
|
+ case CLOCK_EVT_MODE_UNUSED:
|
||
|
|
+ case CLOCK_EVT_MODE_SHUTDOWN:
|
||
|
|
+ break;
|
||
|
|
+ }
|
||
|
|
+ writel_relaxed(ctrl, event_base + TIMER_ENABLE);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static struct clock_event_device __percpu *msm_evt;
|
||
|
|
+
|
||
|
|
+static void __iomem *source_base;
|
||
|
|
+
|
||
|
|
+static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
|
||
|
|
+{
|
||
|
|
+ return readl_relaxed(source_base + TIMER_COUNT_VAL);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
|
||
|
|
+{
|
||
|
|
+ /*
|
||
|
|
+ * Shift timer count down by a constant due to unreliable lower bits
|
||
|
|
+ * on some targets.
|
||
|
|
+ */
|
||
|
|
+ return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static struct clocksource msm_clocksource = {
|
||
|
|
+ .name = "dg_timer",
|
||
|
|
+ .rating = 300,
|
||
|
|
+ .read = msm_read_timer_count,
|
||
|
|
+ .mask = CLOCKSOURCE_MASK(32),
|
||
|
|
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||
|
|
+};
|
||
|
|
+
|
||
|
|
+static int msm_timer_irq;
|
||
|
|
+static int msm_timer_has_ppi;
|
||
|
|
+
|
||
|
|
+static int msm_local_timer_setup(struct clock_event_device *evt)
|
||
|
|
+{
|
||
|
|
+ int cpu = smp_processor_id();
|
||
|
|
+ int err;
|
||
|
|
+
|
||
|
|
+ evt->irq = msm_timer_irq;
|
||
|
|
+ evt->name = "msm_timer";
|
||
|
|
+ evt->features = CLOCK_EVT_FEAT_ONESHOT;
|
||
|
|
+ evt->rating = 200;
|
||
|
|
+ evt->set_mode = msm_timer_set_mode;
|
||
|
|
+ evt->set_next_event = msm_timer_set_next_event;
|
||
|
|
+ evt->cpumask = cpumask_of(cpu);
|
||
|
|
+
|
||
|
|
+ clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
|
||
|
|
+
|
||
|
|
+ if (msm_timer_has_ppi) {
|
||
|
|
+ enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
|
||
|
|
+ } else {
|
||
|
|
+ err = request_irq(evt->irq, msm_timer_interrupt,
|
||
|
|
+ IRQF_TIMER | IRQF_NOBALANCING |
|
||
|
|
+ IRQF_TRIGGER_RISING, "gp_timer", evt);
|
||
|
|
+ if (err)
|
||
|
|
+ pr_err("request_irq failed\n");
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static void msm_local_timer_stop(struct clock_event_device *evt)
|
||
|
|
+{
|
||
|
|
+ evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
|
||
|
|
+ disable_percpu_irq(evt->irq);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static int msm_timer_cpu_notify(struct notifier_block *self,
|
||
|
|
+ unsigned long action, void *hcpu)
|
||
|
|
+{
|
||
|
|
+ /*
|
||
|
|
+ * Grab cpu pointer in each case to avoid spurious
|
||
|
|
+ * preemptible warnings
|
||
|
|
+ */
|
||
|
|
+ switch (action & ~CPU_TASKS_FROZEN) {
|
||
|
|
+ case CPU_STARTING:
|
||
|
|
+ msm_local_timer_setup(this_cpu_ptr(msm_evt));
|
||
|
|
+ break;
|
||
|
|
+ case CPU_DYING:
|
||
|
|
+ msm_local_timer_stop(this_cpu_ptr(msm_evt));
|
||
|
|
+ break;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ return NOTIFY_OK;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static struct notifier_block msm_timer_cpu_nb = {
|
||
|
|
+ .notifier_call = msm_timer_cpu_notify,
|
||
|
|
+};
|
||
|
|
+
|
||
|
|
+static u64 notrace msm_sched_clock_read(void)
|
||
|
|
+{
|
||
|
|
+ return msm_clocksource.read(&msm_clocksource);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
|
||
|
|
+ bool percpu)
|
||
|
|
+{
|
||
|
|
+ struct clocksource *cs = &msm_clocksource;
|
||
|
|
+ int res = 0;
|
||
|
|
+
|
||
|
|
+ msm_timer_irq = irq;
|
||
|
|
+ msm_timer_has_ppi = percpu;
|
||
|
|
+
|
||
|
|
+ msm_evt = alloc_percpu(struct clock_event_device);
|
||
|
|
+ if (!msm_evt) {
|
||
|
|
+ pr_err("memory allocation failed for clockevents\n");
|
||
|
|
+ goto err;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ if (percpu)
|
||
|
|
+ res = request_percpu_irq(irq, msm_timer_interrupt,
|
||
|
|
+ "gp_timer", msm_evt);
|
||
|
|
+
|
||
|
|
+ if (res) {
|
||
|
|
+ pr_err("request_percpu_irq failed\n");
|
||
|
|
+ } else {
|
||
|
|
+ res = register_cpu_notifier(&msm_timer_cpu_nb);
|
||
|
|
+ if (res) {
|
||
|
|
+ free_percpu_irq(irq, msm_evt);
|
||
|
|
+ goto err;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ /* Immediately configure the timer on the boot CPU */
|
||
|
|
+ msm_local_timer_setup(__this_cpu_ptr(msm_evt));
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+err:
|
||
|
|
+ writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
|
||
|
|
+ res = clocksource_register_hz(cs, dgt_hz);
|
||
|
|
+ if (res)
|
||
|
|
+ pr_err("clocksource_register failed\n");
|
||
|
|
+ sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+#ifdef CONFIG_OF
|
||
|
|
+static void __init msm_dt_timer_init(struct device_node *np)
|
||
|
|
+{
|
||
|
|
+ u32 freq;
|
||
|
|
+ int irq;
|
||
|
|
+ struct resource res;
|
||
|
|
+ u32 percpu_offset;
|
||
|
|
+ void __iomem *base;
|
||
|
|
+ void __iomem *cpu0_base;
|
||
|
|
+
|
||
|
|
+ base = of_iomap(np, 0);
|
||
|
|
+ if (!base) {
|
||
|
|
+ pr_err("Failed to map event base\n");
|
||
|
|
+ return;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ /* We use GPT0 for the clockevent */
|
||
|
|
+ irq = irq_of_parse_and_map(np, 1);
|
||
|
|
+ if (irq <= 0) {
|
||
|
|
+ pr_err("Can't get irq\n");
|
||
|
|
+ return;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ /* We use CPU0's DGT for the clocksource */
|
||
|
|
+ if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
|
||
|
|
+ percpu_offset = 0;
|
||
|
|
+
|
||
|
|
+ if (of_address_to_resource(np, 0, &res)) {
|
||
|
|
+ pr_err("Failed to parse DGT resource\n");
|
||
|
|
+ return;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
|
||
|
|
+ if (!cpu0_base) {
|
||
|
|
+ pr_err("Failed to map source base\n");
|
||
|
|
+ return;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ if (of_property_read_u32(np, "clock-frequency", &freq)) {
|
||
|
|
+ pr_err("Unknown frequency\n");
|
||
|
|
+ return;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ event_base = base + 0x4;
|
||
|
|
+ sts_base = base + 0x88;
|
||
|
|
+ source_base = cpu0_base + 0x24;
|
||
|
|
+ freq /= 4;
|
||
|
|
+ writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
|
||
|
|
+
|
||
|
|
+ msm_timer_init(freq, 32, irq, !!percpu_offset);
|
||
|
|
+}
|
||
|
|
+CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
|
||
|
|
+CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
|
||
|
|
+#endif
|
||
|
|
+
|
||
|
|
+static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
|
||
|
|
+ u32 sts)
|
||
|
|
+{
|
||
|
|
+ void __iomem *base;
|
||
|
|
+
|
||
|
|
+ base = ioremap(addr, SZ_256);
|
||
|
|
+ if (!base) {
|
||
|
|
+ pr_err("Failed to map timer base\n");
|
||
|
|
+ return -ENOMEM;
|
||
|
|
+ }
|
||
|
|
+ event_base = base + event;
|
||
|
|
+ source_base = base + source;
|
||
|
|
+ if (sts)
|
||
|
|
+ sts_base = base + sts;
|
||
|
|
+
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+void __init msm7x01_timer_init(void)
|
||
|
|
+{
|
||
|
|
+ struct clocksource *cs = &msm_clocksource;
|
||
|
|
+
|
||
|
|
+ if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
|
||
|
|
+ return;
|
||
|
|
+ cs->read = msm_read_timer_count_shift;
|
||
|
|
+ cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
|
||
|
|
+ /* 600 KHz */
|
||
|
|
+ msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
|
||
|
|
+ false);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+void __init msm7x30_timer_init(void)
|
||
|
|
+{
|
||
|
|
+ if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
|
||
|
|
+ return;
|
||
|
|
+ msm_timer_init(24576000 / 4, 32, 1, false);
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+void __init qsd8x50_timer_init(void)
|
||
|
|
+{
|
||
|
|
+ if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
|
||
|
|
+ return;
|
||
|
|
+ msm_timer_init(19200000 / 4, 32, 7, false);
|
||
|
|
+}
|
||
|
|
--
|
||
|
|
1.7.10.4
|
||
|
|
|