mirror of https://github.com/hak5/openwrt-owl.git
49 lines
1.5 KiB
Diff
49 lines
1.5 KiB
Diff
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From 6c23e1fa6bd220b8f5665c150c83d4c016d95482 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Thu, 7 Nov 2013 12:01:48 +0100
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Subject: [PATCH] ARM: sun7i: a20: Add support for the High Speed Timers
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The Allwinner A20 has support for four high speed timers. Apart for the
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number of timers (4 vs 2), it's basically the same logic than the high
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speed timers found in the sun5i chips.
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Now that we have a driver to support it, we can enable them in the
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device tree.
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[dlezcano] : Fixed conflict with 428abbb8 "Enable the I2C controllers"
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Tested-by: Emilio López <emilio@elopez.com.ar>
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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---
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arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++
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1 file changed, 10 insertions(+)
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diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
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index 93f7f96..c74147a 100644
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--- a/arch/arm/boot/dts/sun7i-a20.dtsi
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+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -405,6 +405,16 @@
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status = "disabled";
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};
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+ hstimer@01c60000 {
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+ compatible = "allwinner,sun7i-a20-hstimer";
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+ reg = <0x01c60000 0x1000>;
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+ interrupts = <0 81 1>,
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+ <0 82 1>,
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+ <0 83 1>,
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+ <0 84 1>;
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+ clocks = <&ahb_gates 28>;
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+ };
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+
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gic: interrupt-controller@01c81000 {
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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reg = <0x01c81000 0x1000>,
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--
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1.8.5.1
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