mirror of https://github.com/hak5/openwrt-owl.git
46 lines
1.5 KiB
Diff
46 lines
1.5 KiB
Diff
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From 05d6c964722224e8cf2902606744e29a835e7d5f Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 3 Dec 2012 21:35:01 +0100
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Subject: [PATCH 102/123] MIPS: lantiq: add GPHY clock gate bits
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Explicitly enable the clock gate of the internal GPHYs found on xrx200.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/lantiq/xway/reset.c | 9 +++++++++
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arch/mips/lantiq/xway/sysctrl.c | 1 +
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2 files changed, 10 insertions(+)
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--- a/arch/mips/lantiq/xway/reset.c
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+++ b/arch/mips/lantiq/xway/reset.c
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@@ -78,10 +78,19 @@ static struct ltq_xrx200_gphy_reset {
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/* reset and boot a gphy. these phys only exist on xrx200 SoC */
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int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
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{
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+ struct clk *clk;
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+
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if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
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dev_err(dev, "this SoC has no GPHY\n");
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return -EINVAL;
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}
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+
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+ clk = clk_get_sys("1f203000.rcu", "gphy");
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+ if (IS_ERR(clk))
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+ return PTR_ERR(clk);
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+
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+ clk_enable(clk);
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+
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if (id > 1) {
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dev_err(dev, "%u is an invalid gphy id\n", id);
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return -EINVAL;
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -374,6 +374,7 @@ void __init ltq_soc_init(void)
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PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
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PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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PMU_PPE_QSB | PMU_PPE_TOP);
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+ clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);
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} else if (of_machine_is_compatible("lantiq,ar9")) {
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clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
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ltq_ar9_fpi_hz());
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