mirror of https://github.com/hak5/openwrt-owl.git
710 lines
19 KiB
Diff
710 lines
19 KiB
Diff
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From c8c69923236f2f3f184ddcc7eb41c113b5cc3223 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 27 Jul 2014 10:57:40 +0100
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Subject: [PATCH 12/57] MIPS: ralink: add MT7621 support
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/include/asm/gic.h | 4 +
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arch/mips/include/asm/mach-ralink/irq.h | 9 +
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arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
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arch/mips/kernel/vmlinux.lds.S | 1 +
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arch/mips/ralink/Kconfig | 18 ++
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arch/mips/ralink/Makefile | 7 +-
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arch/mips/ralink/Platform | 5 +
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arch/mips/ralink/irq-gic.c | 271 ++++++++++++++++++++++++++++
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arch/mips/ralink/malta-amon.c | 81 +++++++++
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arch/mips/ralink/mt7621.c | 183 +++++++++++++++++++
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10 files changed, 617 insertions(+), 1 deletion(-)
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create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
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create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
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create mode 100644 arch/mips/ralink/irq-gic.c
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create mode 100644 arch/mips/ralink/malta-amon.c
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create mode 100644 arch/mips/ralink/mt7621.c
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ralink/irq.h
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@@ -0,0 +1,9 @@
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+#ifndef __ASM_MACH_RALINK_IRQ_H
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+#define __ASM_MACH_RALINK_IRQ_H
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+
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+#define GIC_NUM_INTRS 64
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+#define NR_IRQS 256
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+
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+#include_next <irq.h>
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+
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+#endif
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
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@@ -0,0 +1,39 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Parts of this file are based on Ralink's 2.6.21 BSP
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+ *
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+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#ifndef _MT7621_REGS_H_
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+#define _MT7621_REGS_H_
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+
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+#define MT7621_SYSC_BASE 0x1E000000
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+
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+#define SYSC_REG_CHIP_NAME0 0x00
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+#define SYSC_REG_CHIP_NAME1 0x04
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+#define SYSC_REG_CHIP_REV 0x0c
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+#define SYSC_REG_SYSTEM_CONFIG0 0x10
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+#define SYSC_REG_SYSTEM_CONFIG1 0x14
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+
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+#define CHIP_REV_PKG_MASK 0x1
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+#define CHIP_REV_PKG_SHIFT 16
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+#define CHIP_REV_VER_MASK 0xf
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+#define CHIP_REV_VER_SHIFT 8
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+#define CHIP_REV_ECO_MASK 0xf
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+
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+#define MT7621_DRAM_BASE 0x0
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+#define MT7621_DDR2_SIZE_MIN 32
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+#define MT7621_DDR2_SIZE_MAX 256
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+
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+#define MT7621_CHIP_NAME0 0x3637544D
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+#define MT7621_CHIP_NAME1 0x20203132
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+
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+#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
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+
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+#endif
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--- a/arch/mips/kernel/vmlinux.lds.S
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+++ b/arch/mips/kernel/vmlinux.lds.S
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@@ -51,6 +51,7 @@ SECTIONS
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/* read-only */
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_text = .; /* Text and read-only data */
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.text : {
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+ /*. = . + 0x8000; */
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TEXT_TEXT
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SCHED_TEXT
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LOCK_TEXT
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--- a/arch/mips/ralink/Kconfig
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+++ b/arch/mips/ralink/Kconfig
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@@ -7,6 +7,11 @@ config CLKEVT_RT3352
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select CLKSRC_OF
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select CLKSRC_MMIO
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+config IRQ_INTC
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+ bool
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+ default y
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+ depends on !SOC_MT7621
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+
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choice
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prompt "Ralink SoC selection"
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default SOC_RT305X
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@@ -28,6 +33,15 @@ choice
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config SOC_MT7620
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bool "MT7620"
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+ config SOC_MT7621
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+ bool "MT7621"
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+ select MIPS_CPU_SCACHE
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+ select SYS_SUPPORTS_MULTITHREADING
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+ select SYS_SUPPORTS_SMP
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+ select SYS_SUPPORTS_MIPS_CMP
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+ select IRQ_GIC
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+ select HW_HAS_PCI
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+
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endchoice
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choice
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@@ -59,6 +73,10 @@ choice
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depends on SOC_MT7620
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select BUILTIN_DTB
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+ config DTB_MT7621_EVAL
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+ bool "MT7621 eval kit"
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+ depends on SOC_MT7621
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+
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endchoice
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endif
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--- a/arch/mips/ralink/Makefile
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+++ b/arch/mips/ralink/Makefile
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@@ -6,16 +6,21 @@
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# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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-obj-y := prom.o of.o reset.o clk.o irq.o timer.o
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+obj-y := prom.o of.o reset.o clk.o timer.o
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obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
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obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
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+obj-$(CONFIG_IRQ_INTC) += irq.o
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+obj-$(CONFIG_IRQ_GIC) += irq-gic.o
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+obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
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+
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obj-$(CONFIG_SOC_RT288X) += rt288x.o
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obj-$(CONFIG_SOC_RT305X) += rt305x.o
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obj-$(CONFIG_SOC_RT3883) += rt3883.o
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obj-$(CONFIG_SOC_MT7620) += mt7620.o
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+obj-$(CONFIG_SOC_MT7621) += mt7621.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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--- a/arch/mips/ralink/Platform
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+++ b/arch/mips/ralink/Platform
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@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
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#
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load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
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cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
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+
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+# Ralink MT7621
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+#
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+load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
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+cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
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--- /dev/null
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+++ b/arch/mips/ralink/irq-gic.c
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@@ -0,0 +1,271 @@
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+#include <linux/init.h>
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+#include <linux/sched.h>
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+#include <linux/slab.h>
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+#include <linux/interrupt.h>
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+#include <linux/kernel_stat.h>
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+#include <linux/hardirq.h>
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+#include <linux/preempt.h>
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+#include <linux/irqdomain.h>
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+#include <linux/of_platform.h>
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+#include <linux/of_address.h>
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+#include <linux/of_irq.h>
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+
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+#include <asm/irq_cpu.h>
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+#include <asm/mipsregs.h>
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+
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+#include <asm/irq.h>
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+#include <asm/setup.h>
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+
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+#include <asm/gic.h>
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+#include <asm/gcmpregs.h>
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+
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+#include <asm/mach-ralink/mt7621.h>
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+
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+unsigned long _gcmp_base;
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+static int gic_resched_int_base = 56;
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+static int gic_call_int_base = 60;
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+static struct irq_chip *irq_gic;
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+static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
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+
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+#if defined(CONFIG_MIPS_MT_SMP)
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+static int gic_resched_int_base;
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+static int gic_call_int_base;
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+
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+#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
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+#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
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+
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+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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+{
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+ scheduler_ipi();
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static irqreturn_t
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+ipi_call_interrupt(int irq, void *dev_id)
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+{
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+ smp_call_function_interrupt();
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static struct irqaction irq_resched = {
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+ .handler = ipi_resched_interrupt,
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+ .flags = IRQF_DISABLED|IRQF_PERCPU,
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+ .name = "ipi resched"
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+};
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+
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+static struct irqaction irq_call = {
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+ .handler = ipi_call_interrupt,
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+ .flags = IRQF_DISABLED|IRQF_PERCPU,
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+ .name = "ipi call"
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+};
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+
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+#endif
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+
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+static void __init
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+gic_fill_map(void)
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
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+ gic_intr_map[i].cpunum = 0;
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+ gic_intr_map[i].pin = GIC_CPU_INT0;
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+ gic_intr_map[i].polarity = GIC_POL_POS;
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+ gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
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+ gic_intr_map[i].flags = GIC_FLAG_IPI;
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+ }
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+
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+#if defined(CONFIG_MIPS_MT_SMP)
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+ {
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+ int cpu;
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+
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+ gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
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+ gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
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+
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+ i = gic_resched_int_base;
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+
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+ for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
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+ gic_intr_map[i + cpu].cpunum = cpu;
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+ gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
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+ gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
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+
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+ gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
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+ gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
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+ gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
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+ }
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+ }
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+#endif
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+}
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+
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+void
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+gic_irq_ack(struct irq_data *d)
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+{
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+ int irq = (d->irq - gic_irq_base);
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+
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+ GIC_CLR_INTR_MASK(irq);
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+
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+ if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
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+ GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
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+}
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+
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+void
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+gic_finish_irq(struct irq_data *d)
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+{
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+ GIC_SET_INTR_MASK(d->irq - gic_irq_base);
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+}
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+
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+void __init
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+gic_platform_init(int irqs, struct irq_chip *irq_controller)
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+{
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+ irq_gic = irq_controller;
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+}
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+
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+static void
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+gic_irqdispatch(void)
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+{
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+ unsigned int irq = gic_get_int();
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+
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+ if (likely(irq < GIC_NUM_INTRS))
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+ do_IRQ(MIPS_GIC_IRQ_BASE + irq);
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+ else {
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+ pr_debug("Spurious GIC Interrupt!\n");
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+ spurious_interrupt();
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+ }
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+
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+}
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+
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+static void
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+vi_timer_irqdispatch(void)
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+{
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+ do_IRQ(cp0_compare_irq);
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+}
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+
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+#if defined(CONFIG_MIPS_MT_SMP)
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+unsigned int
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+plat_ipi_call_int_xlate(unsigned int cpu)
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+{
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+ return GIC_CALL_INT(cpu);
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+}
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+
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+unsigned int
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+plat_ipi_resched_int_xlate(unsigned int cpu)
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+{
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+ return GIC_RESCHED_INT(cpu);
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+}
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+#endif
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+
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+asmlinkage void
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+plat_irq_dispatch(void)
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+{
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+ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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+
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+ if (unlikely(!pending)) {
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+ pr_err("Spurious CP0 Interrupt!\n");
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+ spurious_interrupt();
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+ } else {
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+ if (pending & CAUSEF_IP7)
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+ do_IRQ(cp0_compare_irq);
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+
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+ if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
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+ gic_irqdispatch();
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+ }
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+}
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+
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+unsigned int __cpuinit
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+get_c0_compare_int(void)
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+{
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+ return CP0_LEGACY_COMPARE_IRQ;
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+}
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+
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+static int
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+gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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+{
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+ irq_set_chip_and_handler(irq, irq_gic,
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+#if defined(CONFIG_MIPS_MT_SMP)
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+ (hw >= gic_resched_int_base) ?
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+ handle_percpu_irq :
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+#endif
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+ handle_level_irq);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops irq_domain_ops = {
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+ .xlate = irq_domain_xlate_onecell,
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+ .map = gic_map,
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+};
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+
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+static int __init
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+of_gic_init(struct device_node *node,
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+ struct device_node *parent)
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+{
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+ struct irq_domain *domain;
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+ struct resource gcmp = { 0 }, gic = { 0 };
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+ unsigned int gic_rev;
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+ int i;
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+
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+ if (of_address_to_resource(node, 0, &gic))
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+ panic("Failed to get gic memory range");
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+ if (request_mem_region(gic.start, resource_size(&gic),
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+ gic.name) < 0)
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+ panic("Failed to request gic memory");
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+ if (of_address_to_resource(node, 2, &gcmp))
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+ panic("Failed to get gic memory range");
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+ if (request_mem_region(gcmp.start, resource_size(&gcmp),
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+ gcmp.name) < 0)
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+ panic("Failed to request gcmp memory");
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+
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+ _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
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+ if (!_gcmp_base)
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+ panic("Failed to remap gcmp memory\n");
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+
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||
|
+ if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
|
||
|
+ panic("Failed to find gcmp core\n");
|
||
|
+
|
||
|
+ /* tell the gcmp where to find the gic */
|
||
|
+ GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
|
||
|
+ gic_present = 1;
|
||
|
+ if (cpu_has_vint) {
|
||
|
+ set_vi_handler(2, gic_irqdispatch);
|
||
|
+ set_vi_handler(3, gic_irqdispatch);
|
||
|
+ set_vi_handler(4, gic_irqdispatch);
|
||
|
+ set_vi_handler(7, vi_timer_irqdispatch);
|
||
|
+ }
|
||
|
+
|
||
|
+ gic_fill_map();
|
||
|
+
|
||
|
+ gic_init(gic.start, resource_size(&gic), gic_intr_map,
|
||
|
+ ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
|
||
|
+
|
||
|
+ GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
|
||
|
+ pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
|
||
|
+
|
||
|
+ domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
|
||
|
+ 0, &irq_domain_ops, NULL);
|
||
|
+ if (!domain)
|
||
|
+ panic("Failed to add irqdomain");
|
||
|
+
|
||
|
+#if defined(CONFIG_MIPS_MT_SMP)
|
||
|
+ for (i = 0; i < nr_cpu_ids; i++) {
|
||
|
+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
|
||
|
+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
|
||
|
+ }
|
||
|
+#endif
|
||
|
+
|
||
|
+ change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
|
||
|
+ STATUSF_IP2);
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static struct of_device_id __initdata of_irq_ids[] = {
|
||
|
+ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
|
||
|
+ { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
|
||
|
+ {},
|
||
|
+};
|
||
|
+
|
||
|
+void __init
|
||
|
+arch_init_irq(void)
|
||
|
+{
|
||
|
+ of_irq_init(of_irq_ids);
|
||
|
+}
|
||
|
--- /dev/null
|
||
|
+++ b/arch/mips/ralink/malta-amon.c
|
||
|
@@ -0,0 +1,81 @@
|
||
|
+/*
|
||
|
+ * Copyright (C) 2007 MIPS Technologies, Inc.
|
||
|
+ * All rights reserved.
|
||
|
+
|
||
|
+ * This program is free software; you can distribute it and/or modify it
|
||
|
+ * under the terms of the GNU General Public License (Version 2) as
|
||
|
+ * published by the Free Software Foundation.
|
||
|
+ *
|
||
|
+ * This program is distributed in the hope it will be useful, but WITHOUT
|
||
|
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||
|
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||
|
+ * for more details.
|
||
|
+ *
|
||
|
+ * You should have received a copy of the GNU General Public License along
|
||
|
+ * with this program; if not, write to the Free Software Foundation, Inc.,
|
||
|
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||
|
+ *
|
||
|
+ * Arbitrary Monitor interface
|
||
|
+ */
|
||
|
+
|
||
|
+#include <linux/kernel.h>
|
||
|
+#include <linux/init.h>
|
||
|
+#include <linux/smp.h>
|
||
|
+
|
||
|
+#include <asm/addrspace.h>
|
||
|
+#include <asm/mips-boards/launch.h>
|
||
|
+#include <asm/mipsmtregs.h>
|
||
|
+
|
||
|
+int amon_cpu_avail(int cpu)
|
||
|
+{
|
||
|
+ struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
|
||
|
+
|
||
|
+ if (cpu < 0 || cpu >= NCPULAUNCH) {
|
||
|
+ pr_debug("avail: cpu%d is out of range\n", cpu);
|
||
|
+ return 0;
|
||
|
+ }
|
||
|
+
|
||
|
+ launch += cpu;
|
||
|
+ if (!(launch->flags & LAUNCH_FREADY)) {
|
||
|
+ pr_debug("avail: cpu%d is not ready\n", cpu);
|
||
|
+ return 0;
|
||
|
+ }
|
||
|
+ if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
|
||
|
+ pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
|
||
|
+ return 0;
|
||
|
+ }
|
||
|
+
|
||
|
+ return 1;
|
||
|
+}
|
||
|
+
|
||
|
+void amon_cpu_start(int cpu,
|
||
|
+ unsigned long pc, unsigned long sp,
|
||
|
+ unsigned long gp, unsigned long a0)
|
||
|
+{
|
||
|
+ volatile struct cpulaunch *launch =
|
||
|
+ (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
|
||
|
+
|
||
|
+ if (!amon_cpu_avail(cpu))
|
||
|
+ return;
|
||
|
+ if (cpu == smp_processor_id()) {
|
||
|
+ pr_debug("launch: I am cpu%d!\n", cpu);
|
||
|
+ return;
|
||
|
+ }
|
||
|
+ launch += cpu;
|
||
|
+
|
||
|
+ pr_debug("launch: starting cpu%d\n", cpu);
|
||
|
+
|
||
|
+ launch->pc = pc;
|
||
|
+ launch->gp = gp;
|
||
|
+ launch->sp = sp;
|
||
|
+ launch->a0 = a0;
|
||
|
+
|
||
|
+ smp_wmb(); /* Target must see parameters before go */
|
||
|
+ launch->flags |= LAUNCH_FGO;
|
||
|
+ smp_wmb(); /* Target must see go before we poll */
|
||
|
+
|
||
|
+ while ((launch->flags & LAUNCH_FGONE) == 0)
|
||
|
+ ;
|
||
|
+ smp_rmb(); /* Target will be updating flags soon */
|
||
|
+ pr_debug("launch: cpu%d gone!\n", cpu);
|
||
|
+}
|
||
|
--- /dev/null
|
||
|
+++ b/arch/mips/ralink/mt7621.c
|
||
|
@@ -0,0 +1,183 @@
|
||
|
+/*
|
||
|
+ * This program is free software; you can redistribute it and/or modify it
|
||
|
+ * under the terms of the GNU General Public License version 2 as published
|
||
|
+ * by the Free Software Foundation.
|
||
|
+ *
|
||
|
+ * Parts of this file are based on Ralink's 2.6.21 BSP
|
||
|
+ *
|
||
|
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
|
||
|
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||
|
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||
|
+ */
|
||
|
+
|
||
|
+#include <linux/kernel.h>
|
||
|
+#include <linux/init.h>
|
||
|
+#include <linux/module.h>
|
||
|
+#include <asm/gcmpregs.h>
|
||
|
+
|
||
|
+#include <asm/mipsregs.h>
|
||
|
+#include <asm/smp-ops.h>
|
||
|
+#include <asm/mach-ralink/ralink_regs.h>
|
||
|
+#include <asm/mach-ralink/mt7621.h>
|
||
|
+
|
||
|
+#include <pinmux.h>
|
||
|
+
|
||
|
+#include "common.h"
|
||
|
+
|
||
|
+#define SYSC_REG_SYSCFG 0x10
|
||
|
+#define SYSC_REG_CPLL_CLKCFG0 0x2c
|
||
|
+#define SYSC_REG_CUR_CLK_STS 0x44
|
||
|
+#define CPU_CLK_SEL (BIT(30) | BIT(31))
|
||
|
+
|
||
|
+#define MT7621_GPIO_MODE_UART1 1
|
||
|
+#define MT7621_GPIO_MODE_I2C 2
|
||
|
+#define MT7621_GPIO_MODE_UART2 3
|
||
|
+#define MT7621_GPIO_MODE_UART3 5
|
||
|
+#define MT7621_GPIO_MODE_JTAG 7
|
||
|
+#define MT7621_GPIO_MODE_WDT_MASK 0x3
|
||
|
+#define MT7621_GPIO_MODE_WDT_SHIFT 8
|
||
|
+#define MT7621_GPIO_MODE_WDT_GPIO 1
|
||
|
+#define MT7621_GPIO_MODE_PCIE_RST 0
|
||
|
+#define MT7621_GPIO_MODE_PCIE_REF 2
|
||
|
+#define MT7621_GPIO_MODE_PCIE_MASK 0x3
|
||
|
+#define MT7621_GPIO_MODE_PCIE_SHIFT 10
|
||
|
+#define MT7621_GPIO_MODE_PCIE_GPIO 1
|
||
|
+#define MT7621_GPIO_MODE_MDIO 12
|
||
|
+#define MT7621_GPIO_MODE_RGMII1 14
|
||
|
+#define MT7621_GPIO_MODE_RGMII2 15
|
||
|
+#define MT7621_GPIO_MODE_SPI_MASK 0x3
|
||
|
+#define MT7621_GPIO_MODE_SPI_SHIFT 16
|
||
|
+#define MT7621_GPIO_MODE_SPI_GPIO 1
|
||
|
+#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
|
||
|
+#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
|
||
|
+#define MT7621_GPIO_MODE_SDHCI_GPIO 1
|
||
|
+
|
||
|
+static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart", 0, 1, 2) };
|
||
|
+static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
|
||
|
+static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart", 0, 5, 4) };
|
||
|
+static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart", 0, 9, 4) };
|
||
|
+static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
|
||
|
+static struct rt2880_pmx_func wdt_grp[] = {
|
||
|
+ FUNC("wdt rst", 0, 18, 1),
|
||
|
+ FUNC("wdt refclk", 2, 18, 1),
|
||
|
+};
|
||
|
+static struct rt2880_pmx_func pcie_rst_grp[] = {
|
||
|
+ FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
|
||
|
+ FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
|
||
|
+};
|
||
|
+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
|
||
|
+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii", 0, 22, 12) };
|
||
|
+static struct rt2880_pmx_func spi_grp[] = {
|
||
|
+ FUNC("spi", 0, 34, 7),
|
||
|
+ FUNC("nand", 2, 34, 8),
|
||
|
+};
|
||
|
+static struct rt2880_pmx_func sdhci_grp[] = {
|
||
|
+ FUNC("sdhci", 0, 41, 8),
|
||
|
+ FUNC("nand", 2, 41, 8),
|
||
|
+};
|
||
|
+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii", 0, 49, 12) };
|
||
|
+
|
||
|
+static struct rt2880_pmx_group mt7621_pinmux_data[] = {
|
||
|
+ GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
|
||
|
+ GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
|
||
|
+ GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
|
||
|
+ GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
|
||
|
+ GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
|
||
|
+ GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
|
||
|
+ MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
|
||
|
+ GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
|
||
|
+ MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
|
||
|
+ GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
|
||
|
+ GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
|
||
|
+ GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
|
||
|
+ MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
|
||
|
+ GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
|
||
|
+ MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
|
||
|
+ GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
|
||
|
+ { 0 }
|
||
|
+};
|
||
|
+
|
||
|
+void __init ralink_clk_init(void)
|
||
|
+{
|
||
|
+ int cpu_fdiv = 0;
|
||
|
+ int cpu_ffrac = 0;
|
||
|
+ int fbdiv = 0;
|
||
|
+ u32 clk_sts, syscfg;
|
||
|
+ u8 clk_sel = 0, xtal_mode;
|
||
|
+ u32 cpu_clk;
|
||
|
+
|
||
|
+ if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
|
||
|
+ clk_sel = 1;
|
||
|
+
|
||
|
+ switch (clk_sel) {
|
||
|
+ case 0:
|
||
|
+ clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
|
||
|
+ cpu_fdiv = ((clk_sts >> 8) & 0x1F);
|
||
|
+ cpu_ffrac = (clk_sts & 0x1F);
|
||
|
+ cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
|
||
|
+ break;
|
||
|
+
|
||
|
+ case 1:
|
||
|
+ fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
|
||
|
+ syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
|
||
|
+ xtal_mode = (syscfg >> 6) & 0x7;
|
||
|
+ if(xtal_mode >= 6) { //25Mhz Xtal
|
||
|
+ cpu_clk = 25 * fbdiv * 1000 * 1000;
|
||
|
+ } else if(xtal_mode >=3) { //40Mhz Xtal
|
||
|
+ cpu_clk = 40 * fbdiv * 1000 * 1000;
|
||
|
+ } else { // 20Mhz Xtal
|
||
|
+ cpu_clk = 20 * fbdiv * 1000 * 1000;
|
||
|
+ }
|
||
|
+ break;
|
||
|
+ }
|
||
|
+ cpu_clk = 880000000;
|
||
|
+ ralink_clk_add("cpu", cpu_clk);
|
||
|
+ ralink_clk_add("1e000b00.spi", 50000000);
|
||
|
+ ralink_clk_add("1e000c00.uartlite", 50000000);
|
||
|
+ ralink_clk_add("1e000d00.uart", 50000000);
|
||
|
+}
|
||
|
+
|
||
|
+void __init ralink_of_remap(void)
|
||
|
+{
|
||
|
+ rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
|
||
|
+ rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
|
||
|
+
|
||
|
+ if (!rt_sysc_membase || !rt_memc_membase)
|
||
|
+ panic("Failed to remap core resources");
|
||
|
+}
|
||
|
+
|
||
|
+void prom_soc_init(struct ralink_soc_info *soc_info)
|
||
|
+{
|
||
|
+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
|
||
|
+ unsigned char *name = NULL;
|
||
|
+ u32 n0;
|
||
|
+ u32 n1;
|
||
|
+ u32 rev;
|
||
|
+
|
||
|
+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
|
||
|
+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
|
||
|
+
|
||
|
+ if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
|
||
|
+ name = "MT7621";
|
||
|
+ soc_info->compatible = "mtk,mt7621-soc";
|
||
|
+ } else {
|
||
|
+ panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
|
||
|
+ }
|
||
|
+
|
||
|
+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
|
||
|
+
|
||
|
+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
|
||
|
+ "Mediatek %s ver:%u eco:%u",
|
||
|
+ name,
|
||
|
+ (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
|
||
|
+ (rev & CHIP_REV_ECO_MASK));
|
||
|
+
|
||
|
+ soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
|
||
|
+ soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
|
||
|
+ soc_info->mem_base = MT7621_DRAM_BASE;
|
||
|
+
|
||
|
+ rt2880_pinmux_data = mt7621_pinmux_data;
|
||
|
+
|
||
|
+ if (register_cmp_smp_ops())
|
||
|
+ panic("failed to register_vsmp_smp_ops()");
|
||
|
+}
|