mirror of https://github.com/hak5/openwrt-owl.git
84 lines
2.9 KiB
Diff
84 lines
2.9 KiB
Diff
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From d2d88e3432d68b11b0add84bd15a3aadaf44f1c1 Mon Sep 17 00:00:00 2001
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From: Yunhui Cui <B56489@freescale.com>
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Date: Mon, 28 Dec 2015 18:25:56 +0800
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Subject: [PATCH 102/113] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a
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There is a hardware feature that qspi_amba_base is added
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internally by SOC design on ls2080a. So as to software, the driver
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need support to the feature.
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Signed-off-by: Yunhui Cui <B56489@freescale.com>
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Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
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---
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drivers/mtd/spi-nor/fsl-quadspi.c | 24 ++++++++++++++++++++++--
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1 file changed, 22 insertions(+), 2 deletions(-)
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--- a/drivers/mtd/spi-nor/fsl-quadspi.c
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+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
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@@ -41,6 +41,8 @@
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#define QUADSPI_QUIRK_TKT253890 (1 << 2)
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/* Controller cannot wake up from wait mode, TKT245618 */
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#define QUADSPI_QUIRK_TKT245618 (1 << 3)
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+/* QSPI_AMBA_BASE is internally added by SOC design */
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+#define QUADSPI_AMBA_BASE_INTERNAL (0x10000)
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/* The registers */
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#define QUADSPI_MCR 0x00
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@@ -217,6 +219,7 @@ enum fsl_qspi_devtype {
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FSL_QUADSPI_IMX7D,
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FSL_QUADSPI_IMX6UL,
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FSL_QUADSPI_LS1021A,
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+ FSL_QUADSPI_LS2080A,
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};
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struct fsl_qspi_devtype_data {
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@@ -270,6 +273,14 @@ static struct fsl_qspi_devtype_data ls10
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.driver_data = 0,
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};
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+static struct fsl_qspi_devtype_data ls2080a_data = {
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+ .devtype = FSL_QUADSPI_LS2080A,
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+ .rxfifo = 128,
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+ .txfifo = 64,
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+ .ahb_buf_size = 1024,
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+ .driver_data = QUADSPI_AMBA_BASE_INTERNAL,
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+};
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+
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#define FSL_QSPI_MAX_CHIP 4
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struct fsl_qspi {
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struct spi_nor nor[FSL_QSPI_MAX_CHIP];
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@@ -312,6 +323,11 @@ static inline int needs_wakeup_wait_mode
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return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
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}
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+static inline int has_added_amba_base_internal(struct fsl_qspi *q)
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+{
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+ return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
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+}
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+
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/*
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* R/W functions for big- or little-endian registers:
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* The qSPI controller's endian is independent of the CPU core's endian.
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@@ -558,8 +574,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
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/* save the reg */
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reg = qspi_readl(q, base + QUADSPI_MCR);
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- qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
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- base + QUADSPI_SFAR);
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+ if (has_added_amba_base_internal(q))
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+ qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR);
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+ else
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+ qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
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+ base + QUADSPI_SFAR);
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qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
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base + QUADSPI_RBCT);
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qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
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@@ -849,6 +868,7 @@ static const struct of_device_id fsl_qsp
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{ .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
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{ .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
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{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
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+ { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
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