mirror of https://github.com/hak5/openwrt-owl.git
97 lines
3.4 KiB
Diff
97 lines
3.4 KiB
Diff
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From 76a9fed9e5580945827a82963ac7315186fd0ebe Mon Sep 17 00:00:00 2001
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From: Luka Perkov <luka@openwrt.org>
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Date: Mon, 11 Nov 2013 06:45:44 +0100
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Subject: [PATCH 1/9] cosmetic: kirkwood: style fixes in kwbimage.cfg files
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When diffing through the changes only the relevant changes
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should be displayed.
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Signed-off-by: Luka Perkov <luka@openwrt.org>
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---
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board/iomega/iconnect/kwbimage.cfg | 4 ++--
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board/raidsonic/ib62x0/kwbimage.cfg | 22 +++++++++++-----------
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2 files changed, 13 insertions(+), 13 deletions(-)
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--- a/board/iomega/iconnect/kwbimage.cfg
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+++ b/board/iomega/iconnect/kwbimage.cfg
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@@ -20,7 +20,7 @@ NAND_PAGE_SIZE 0x0800
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# Configure RGMII-0 interface pad voltage to 1.8V
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DATA 0xffd100e0 0x1b1b1b9b
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-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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+# Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xffd01400 0x43000c30 # DDR Configuration register
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# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
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# bit23-14: 0x0,
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@@ -87,7 +87,7 @@ DATA 0xffd0141c 0x00000c52 # DDR Mode
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# bit6-4: 0x4, CL=5
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# bit7: 0x0, TestMode=0 normal
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# bit8: 0x0, DLL reset=0 normal
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-# bit11-9: 0x6, auto-precharge write recovery ????????????
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+# bit11-9: 0x6, auto-precharge write recovery
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# bit12: 0x0, PD must be zero
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# bit31-13: 0x0, required
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--- a/board/raidsonic/ib62x0/kwbimage.cfg
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+++ b/board/raidsonic/ib62x0/kwbimage.cfg
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@@ -11,7 +11,7 @@
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#
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# Boot Media configurations
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-BOOT_FROM nand # change from nand to uart if building UART image
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+BOOT_FROM nand
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NAND_ECC_MODE default
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NAND_PAGE_SIZE 0x0800
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@@ -21,12 +21,12 @@ NAND_PAGE_SIZE 0x0800
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# Configure RGMII-0 interface pad voltage to 1.8V
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DATA 0xffd100e0 0x1b1b1b9b
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-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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+# Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xffd01400 0x43000c30 # DDR Configuration register
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# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
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# bit23-14: 0x0,
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-# bit24: 0x1, enable exit self refresh mode on DDR access
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-# bit25: 0x1, required
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+# bit24: 0x1, enable exit self refresh mode on DDR access
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+# bit25: 0x1, required
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# bit29-26: 0x0,
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# bit31-30: 0x1,
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@@ -64,10 +64,10 @@ DATA 0xffd01410 0x0000000c # DDR Address
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# bit3-2: 11, Cs0size (1Gb)
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# bit5-4: 00, Cs1width (x8)
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# bit7-6: 11, Cs1size (1Gb)
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-# bit9-8: 00, Cs2width (nonexistent
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-# bit11-10: 00, Cs2size (nonexistent
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-# bit13-12: 00, Cs3width (nonexistent
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-# bit15-14: 00, Cs3size (nonexistent
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+# bit9-8: 00, Cs2width (nonexistent)
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+# bit11-10: 00, Cs2size (nonexistent)
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+# bit13-12: 00, Cs3width (nonexistent)
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+# bit15-14: 00, Cs3size (nonexistent)
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# bit16: 0, Cs0AddrSel
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# bit17: 0, Cs1AddrSel
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# bit18: 0, Cs2AddrSel
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@@ -88,7 +88,7 @@ DATA 0xffd0141c 0x00000c52 # DDR Mode
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# bit6-4: 0x4, CL=5
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# bit7: 0x0, TestMode=0 normal
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# bit8: 0x0, DLL reset=0 normal
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-# bit11-9: 0x6, auto-precharge write recovery ????????????
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+# bit11-9: 0x6, auto-precharge write recovery
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# bit12: 0x0, PD must be zero
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# bit31-13: 0x0, required
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@@ -148,8 +148,8 @@ DATA 0xffd0149c 0x0000e803 # CPU ODT Con
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DATA 0xffd01480 0x00000001 # DDR Initialization Control
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# bit0: 0x1, enable DDR init upon this register write
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-DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
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-DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
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+DATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register
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+DATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register
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# End of Header extension
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DATA 0x0 0x0
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