mirror of https://github.com/hak5/openwrt-owl.git
57 lines
1.8 KiB
Diff
57 lines
1.8 KiB
Diff
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From ec6f1e53b22d01e628b79b99f7a33960034e97e7 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Mon, 21 Nov 2011 00:53:26 +0100
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Subject: [PATCH 6/7] MIPS: BCM63XX: enable pcie for BCM6362
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The PCIe controller is almost the same as the BCM6328 one, with only
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the SERDES register being at a different location.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 3 ++-
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arch/mips/pci/pci-bcm63xx.c | 11 +++++++++--
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2 files changed, 11 insertions(+), 3 deletions(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1365,7 +1365,8 @@
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/*************************************************************************
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* _REG relative to RSET_MISC
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*************************************************************************/
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-#define MISC_SERDES_CTRL_REG 0x0
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+#define MISC_SERDES_CTRL_6328_REG 0x0
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+#define MISC_SERDES_CTRL_6362_REG 0x4
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#define SERDES_PCIE_EN (1 << 0)
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#define SERDES_PCIE_EXD_EN (1 << 15)
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--- a/arch/mips/pci/pci-bcm63xx.c
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+++ b/arch/mips/pci/pci-bcm63xx.c
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@@ -121,11 +121,17 @@ void __iomem *pci_iospace_start;
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static void __init bcm63xx_reset_pcie(void)
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{
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u32 val;
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+ u32 reg;
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/* enable SERDES */
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- val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
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+ if (BCMCPU_IS_6328())
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+ reg = MISC_SERDES_CTRL_6328_REG;
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+ else
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+ reg = MISC_SERDES_CTRL_6362_REG;
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+
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+ val = bcm_misc_readl(reg);
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val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
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- bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
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+ bcm_misc_writel(val, reg);
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/* reset the PCIe core */
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bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
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@@ -330,6 +336,7 @@ static int __init bcm63xx_pci_init(void)
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switch (bcm63xx_get_cpu_id()) {
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case BCM6328_CPU_ID:
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+ case BCM6362_CPU_ID:
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return bcm63xx_register_pcie();
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case BCM6348_CPU_ID:
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case BCM6358_CPU_ID:
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