mirror of https://github.com/hak5/openwrt-owl.git
42 lines
1.2 KiB
Diff
42 lines
1.2 KiB
Diff
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--- a/arch/arm/mm/cache-fa.S
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+++ b/arch/arm/mm/cache-fa.S
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@@ -24,7 +24,8 @@
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/*
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* The size of one data cache line.
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*/
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-#define CACHE_DLINESIZE 16
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+#define CACHE_DLINESIZE 16
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+#define CACHE_DLINESHIFT 4
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/*
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* The total size of the data cache.
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@@ -169,7 +170,17 @@ ENTRY(fa_flush_kern_dcache_area)
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* - start - virtual start address
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* - end - virtual end address
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*/
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+__flush_whole_dcache:
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+ mcr p15, 0, r0, c7, c14, 0 @ clean/invalidate D cache
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+ mov r0, #0
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+ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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+ mov pc, lr
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+
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fa_dma_inv_range:
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+ sub r3, r1, r0 @ calculate total size
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+ cmp r3, #CACHE_DLIMIT @ total size >= limit?
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+ bhs __flush_whole_dcache @ flush whole D cache
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+
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
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@@ -193,6 +204,10 @@ fa_dma_inv_range:
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* - end - virtual end address
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*/
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fa_dma_clean_range:
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+ sub r3, r1, r0 @ calculate total size
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+ cmp r3, #CACHE_DLIMIT @ total size >= limit?
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+ bhs __flush_whole_dcache @ flush whole D cache
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+
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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