mirror of https://github.com/hak5/openwrt-owl.git
200 lines
5.3 KiB
Diff
200 lines
5.3 KiB
Diff
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From 7008284716403237f6bc7d7590b3ed073555bd56 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Wed, 11 Jan 2012 22:25:11 +0100
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Subject: [PATCH 34/34] spi/ath79: make chipselect logic more flexible
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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arch/mips/ath79/mach-pb44.c | 6 ++
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.../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++-
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drivers/spi/spi-ath79.c | 67 +++++++++++++-------
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8 files changed, 88 insertions(+), 23 deletions(-)
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--- a/arch/mips/ath79/mach-pb44.c
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+++ b/arch/mips/ath79/mach-pb44.c
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@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio
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}
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};
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+static struct ath79_spi_controller_data pb44_spi0_data = {
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+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
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+ .cs_line = 0,
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+};
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+
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static struct spi_board_info pb44_spi_info[] = {
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{
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.bus_num = 0,
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.chip_select = 0,
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.max_speed_hz = 25000000,
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.modalias = "m25p64",
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+ .controller_data = &pb44_spi0_data,
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},
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};
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--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
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@@ -16,8 +16,14 @@ struct ath79_spi_platform_data {
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unsigned num_chipselect;
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};
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+enum ath79_spi_cs_type {
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+ ATH79_SPI_CS_TYPE_INTERNAL,
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+ ATH79_SPI_CS_TYPE_GPIO,
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+};
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+
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struct ath79_spi_controller_data {
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- unsigned gpio;
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+ enum ath79_spi_cs_type cs_type;
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+ unsigned cs_line;
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};
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#endif /* _ATH79_SPI_PLATFORM_H */
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--- a/drivers/spi/spi-ath79.c
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+++ b/drivers/spi/spi-ath79.c
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@@ -33,6 +33,8 @@
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#define ATH79_SPI_RRW_DELAY_FACTOR 12000
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#define MHZ (1000 * 1000)
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+#define ATH79_SPI_CS_LINE_MAX 2
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+
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struct ath79_spi {
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struct spi_bitbang bitbang;
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u32 ioc_base;
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@@ -67,6 +69,7 @@ static void ath79_spi_chipselect(struct
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
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+ struct ath79_spi_controller_data *cdata = spi->controller_data;
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if (is_active) {
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/* set initial clock polarity */
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@@ -78,20 +81,24 @@ static void ath79_spi_chipselect(struct
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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}
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- if (spi->chip_select) {
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- struct ath79_spi_controller_data *cdata = spi->controller_data;
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-
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- /* SPI is normally active-low */
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- gpio_set_value(cdata->gpio, cs_high);
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- } else {
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+ switch (cdata->cs_type) {
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+ case ATH79_SPI_CS_TYPE_INTERNAL:
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if (cs_high)
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- sp->ioc_base |= AR71XX_SPI_IOC_CS0;
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+ sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line);
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else
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- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
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+ sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line);
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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- }
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+ break;
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+ case ATH79_SPI_CS_TYPE_GPIO:
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+ /* SPI is normally active-low */
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+ if (gpio_cansleep(cdata->cs_line))
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+ gpio_set_value_cansleep(cdata->cs_line, cs_high);
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+ else
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+ gpio_set_value(cdata->cs_line, cs_high);
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+ break;
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+ }
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}
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static void ath79_spi_enable(struct ath79_spi *sp)
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@@ -119,14 +126,15 @@ static int ath79_spi_setup_cs(struct spi
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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struct ath79_spi_controller_data *cdata = spi->controller_data;
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+ unsigned long flags;
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int status;
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- if (spi->chip_select && (!cdata || !gpio_is_valid(cdata->gpio)))
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+ if (!cdata)
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return -EINVAL;
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status = 0;
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- if (spi->chip_select) {
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- unsigned long flags;
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+ switch (cdata->cs_type) {
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+ case ATH79_SPI_CS_TYPE_GPIO:
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flags = GPIOF_DIR_OUT;
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if (spi->mode & SPI_CS_HIGH)
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@@ -134,15 +142,21 @@ static int ath79_spi_setup_cs(struct spi
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else
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flags |= GPIOF_INIT_HIGH;
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- status = gpio_request_one(cdata->gpio, flags,
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+ status = gpio_request_one(cdata->cs_line, flags,
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dev_name(&spi->dev));
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- } else {
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+ break;
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+ case ATH79_SPI_CS_TYPE_INTERNAL:
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+ if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX)
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+ status = -EINVAL;
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+ break;
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+
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if (spi->mode & SPI_CS_HIGH)
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sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
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else
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sp->ioc_base |= AR71XX_SPI_IOC_CS0;
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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+ break;
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}
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return status;
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@@ -150,9 +164,19 @@ static int ath79_spi_setup_cs(struct spi
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static void ath79_spi_cleanup_cs(struct spi_device *spi)
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{
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- if (spi->chip_select) {
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- struct ath79_spi_controller_data *cdata = spi->controller_data;
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- gpio_free(cdata->gpio);
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+ struct ath79_spi_controller_data *cdata;
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+
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+ cdata = spi->controller_data;
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+ if (!cdata)
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+ return;
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+
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+ switch (cdata->cs_type) {
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+ case ATH79_SPI_CS_TYPE_INTERNAL:
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+ /* nothing to do */
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+ break;
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+ case ATH79_SPI_CS_TYPE_GPIO:
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+ gpio_free(cdata->cs_line);
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+ break;
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}
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}
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@@ -217,6 +241,10 @@ static int ath79_spi_probe(struct platfo
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unsigned long rate;
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int ret;
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+ pdata = pdev->dev.platform_data;
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+ if (!pdata)
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+ return -EINVAL;
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+
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master = spi_alloc_master(&pdev->dev, sizeof(*sp));
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if (master == NULL) {
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dev_err(&pdev->dev, "failed to allocate spi master\n");
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@@ -226,15 +254,11 @@ static int ath79_spi_probe(struct platfo
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sp = spi_master_get_devdata(master);
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platform_set_drvdata(pdev, sp);
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- pdata = dev_get_platdata(&pdev->dev);
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-
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
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master->setup = ath79_spi_setup;
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master->cleanup = ath79_spi_cleanup;
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- if (pdata) {
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- master->bus_num = pdata->bus_num;
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- master->num_chipselect = pdata->num_chipselect;
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- }
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+ master->bus_num = pdata->bus_num;
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+ master->num_chipselect = pdata->num_chipselect;
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sp->bitbang.master = master;
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sp->bitbang.chipselect = ath79_spi_chipselect;
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