2013-11-15 12:23:17 +00:00
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On OMAP we have co-processor IPs, memory controllers,
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GPIOs which control regulators and power switches to
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PMIC, and SoC internal Bus IPs, some or most of which
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should either not be reset or idled or both at init.
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(In some cases there are erratas which prevent an IP
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from being reset)
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Have a way to pass this information from DT.
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Update the am33xx/omap4 and omap5 dtsi files with the
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new bindings for modules which either should not be
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idled. reset or both. A later patch would cleanup the
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same information that exists today as part of the hwmod
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data files.
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Signed-off-by: Rajendra Nayak <rnayak@ti.com>
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---
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.../devicetree/bindings/arm/omap/omap.txt | 3 ++-
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arch/arm/boot/dts/am33xx.dtsi | 2 ++
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arch/arm/boot/dts/omap4.dtsi | 3 +++
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arch/arm/boot/dts/omap5.dtsi | 2 ++
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4 files changed, 9 insertions(+), 1 deletion(-)
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--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
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+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
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@@ -21,7 +21,8 @@ Required properties:
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Optional properties:
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- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
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during suspend.
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-
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+- ti,no-reset-on-init: When present, the module should not be reset at init
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+- ti,no-idle-on-init: When present, the module should not be idled at init
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Example:
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--- a/arch/arm/boot/dts/am33xx.dtsi
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+++ b/arch/arm/boot/dts/am33xx.dtsi
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2013-11-27 12:34:41 +00:00
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@@ -667,6 +667,7 @@
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2013-11-15 12:23:17 +00:00
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reg = <0x44d00000 0x4000 /* M3 UMEM */
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0x44d80000 0x2000>; /* M3 DMEM */
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ti,hwmods = "wkup_m3";
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+ ti,no-reset-on-init;
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};
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elm: elm@48080000 {
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2013-11-27 12:34:41 +00:00
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@@ -697,6 +698,7 @@
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2013-11-15 12:23:17 +00:00
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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+ ti,no-idle-on-init;
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reg = <0x50000000 0x2000>;
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interrupts = <100>;
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gpmc,num-cs = <7>;
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--- a/arch/arm/boot/dts/omap4.dtsi
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+++ b/arch/arm/boot/dts/omap4.dtsi
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@@ -214,6 +214,7 @@
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <4>;
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ti,hwmods = "gpmc";
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+ ti,no-idle-on-init;
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};
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uart1: serial@4806a000 {
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@@ -492,6 +493,7 @@
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reg = <0x4c000000 0x100>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "emif1";
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+ ti,no-idle-on-init;
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phy-type = <1>;
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hw-caps-read-idle-ctrl;
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hw-caps-ll-interface;
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@@ -503,6 +505,7 @@
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reg = <0x4d000000 0x100>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "emif2";
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+ ti,no-idle-on-init;
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phy-type = <1>;
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hw-caps-read-idle-ctrl;
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hw-caps-ll-interface;
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--- a/arch/arm/boot/dts/omap5.dtsi
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+++ b/arch/arm/boot/dts/omap5.dtsi
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@@ -607,6 +607,7 @@
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emif1: emif@0x4c000000 {
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compatible = "ti,emif-4d5";
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ti,hwmods = "emif1";
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+ ti,no-idle-on-init;
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phy-type = <2>; /* DDR PHY type: Intelli PHY */
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reg = <0x4c000000 0x400>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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@@ -618,6 +619,7 @@
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emif2: emif@0x4d000000 {
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compatible = "ti,emif-4d5";
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ti,hwmods = "emif2";
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+ ti,no-idle-on-init;
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phy-type = <2>; /* DDR PHY type: Intelli PHY */
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reg = <0x4d000000 0x400>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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