ch0ic3/h4cker
1
0
Fork 0
mirror of https://github.com/The-Art-of-Hacking/h4cker.git synced 2024-12-18 10:56:09 +00:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

Update registers.md

Browse Source
This commit is contained in:
Omar Santos 2018-06-26 21:58:40 -04:00 committed by GitHub
parent 055789a512
commit a7eea205f5
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
buffer_overflow_example/registers.md
View File

@ -1,14 +1,8 @@
# Good Information about Registers # Good Information about Registers
x64 extends x86's 8 general-purpose registers to be 64-bit, and adds 8 new 64-bit registers. - Intel's Architecture Documentation: https://software.intel.com/en-us/articles/intel-sdm
The 64-bit registers have names beginning with "r", so for example the 64-bit extension of **eax** is called **rax**. Additional Notes: The x64 architecture extends x86's 8 general-purpose registers to be 64-bit, and adds 8 new 64-bit registers. The 64-bit registers have names beginning with "r", so for example the 64-bit extension of **eax** is called **rax**. The lower 32 bits, 16 bits, and 8 bits of each register are directly addressable in operands. This includes registers, like **esi**, whose lower 8 bits were not previously addressable. The following table specifies the assembly-language names for the lower portions of 64-bit registers.
The lower 32 bits, 16 bits, and 8 bits of each register are directly addressable in operands.
This includes registers, like **esi**, whose lower 8 bits were not previously addressable.
The following table specifies the assembly-language names for the lower portions of 64-bit registers.
<table><colgroup><col width="25%"> <col width="25%"> <col width="25%"> <col width="25%"></colgroup> <table><colgroup><col width="25%"> <col width="25%"> <col width="25%"> <col width="25%"></colgroup>